A typical memory controller of a computer system includes a memory interface, which establishes communication between the memory controller and a memory bus. Data on the memory bus typically is transmitted at very high speeds. Other internal circuitry of the memory controller operates at a different, e.g., lower frequency, as the internal circuitry may handle data in a parallel manner, while data on the memory bus is communicated serially. Thus there can be clock crossing issues between circuitry in different parts of the memory controller.
More specifically, a conventional memory interface of a memory controller may have a core partition, which furnishes the data that is to be written to the memory. An analog partition of the memory interface generates the clock and data signals that appear on the memory bus and an input/output (IO) partition contains deep first-in first-out (FIFO) buffers and circuitry to handle the clock domain transfer between the core and analog partitions. However, the FIFOs can become very large, consuming valuable chip real estate, as well as increasing power consumption levels. Further needed circuitry and the uncertainty of parameters of a particular system operation cause designers to set a fixed transmit clock to transmit data from the IO portion at a level that leads to a high latency (from the time that data is received in the IO portion until it is transmitted onto the interconnect).